1. Field of the Invention
The present invention relates to an amplifier, and more particularly, to an output stage circuit and an operational amplifier thereof.
2. Description of the Related Art
In analog circuit, the output stage circuit plays the role of driving the load in the condition of less gain decreasing.
FIG. 1 illustrates a circuit diagram depicting a complementary metal-oxide semiconductor (CMOS) operational amplifier with class AB output stage 100 in the reference [1]. Referring to FIG. 1, the operational amplifier 10 includes a class AB output stage 100, two resistors R10 and R11, two capacitors C10 and C11, an amplifying circuit A10 and a bias circuit B10, wherein the bias circuit B10 includes two sub bias circuits B10-1 and B10-2. For the explanation of the operation of the operational amplifier 10, in this circuit diagram, and a plurality of nodes A, B, X and Y are marked. The sub bias circuits B10-1 and B10-2 respectively control voltages of nodes A and B through the current sources IB1 and IB2 therein, so as to respectively control the bias voltages of nodes X and Y. Thus, the bias current lout of the class AB output stage 100 is proportional to the currents of IB1 and IB2.
The bias method of the class AB output stage 100 has advantages of fast frequency response. Nevertheless, this circuit scheme must adopt a bias circuit B10 using the folded-cascode configuration for biasing the class AB output stage. According to the description above, apparently, the circuit at least has two disadvantages as follow:
1. The control of steady current is inaccurate due to channel length modulation.
2. This circuit cannot be applied in lower supply voltage due to 2VGS requirement in the nodes A and B. For example, in UMC 0.35 μm fabricating process, the threshold voltage of p-type MOSFET (VTP) is about 0.8V. It should be considered the slow corner effect and the overdrive voltage about 0.1V. Thus, this circuit cannot be operated in the condition of VDD−VSS<2V.
FIG. 2 illustrates a circuit diagram depicting an operational amplifier for improving the operational amplifier of FIG. 1 in the reference [1]. Referring to FIG. 1 and FIG. 2, there are 4 transistors cascaded in the bias circuit B20 in FIG. 2, and comparatively, there are 5 transistors cascaded in the bias circuit B10 in FIG. 1. Apparently, the operational amplifier in FIG. 2 is more proper to be applied in the condition of the low supply voltage. Since the transistors M201 and M202 of the bias circuit B20 is configured as a differential pair, it can control the voltage difference between the node X and the node Y as long as the adapted DC voltage is properly given to the node E. In the small signal operation, the voltages of the node X and the node Y varies in the same phase as the output signal of the amplifying circuit A20. At this time, the voltage of the node A is varied as the voltages of the node X and the node Y, so that the voltage difference between the node X and the node Y is consequentially varied. Therefore, the output signal Vout outputted from the class AB output stage circuit O20 will be distorted.
Reference [1] K. J. de Langen, J. H. Huijsing, “Compact Low-Voltage Power-efficient Operational Amplifier Cells for VLSI”, IEEE Journal of Solid-State Circuits, vol. SC-33, pp. 1482-1496. October 1997.